I'm sorry but everything you said doesn't make any sense in context of hardware design.
There are two ways in which the nodes of your design can obtain new values:
- Through a clock edge
- Through an asynchronous event like the reset
Your expression for that initial value doesn't represent any of those. You need to have an initial state on your design in order to have the proper initial conditions. And that initial state is the reset.
On FPGAs there is a third way for a register to get new values: FPGA configuration. When FPGA is re/configured initial values specified (like in previous post) will be set as value of FF.
There are two ways in which the nodes of your design can obtain new values: - Through a clock edge - Through an asynchronous event like the reset
Your expression for that initial value doesn't represent any of those. You need to have an initial state on your design in order to have the proper initial conditions. And that initial state is the reset.