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Because the chip-makers and chip buyers are using ARM and MIPS in power-efficient SOC's. They could do the same with SPARC. They just didn't for whatever reasons.

Far as power efficiency, kristoffer might be able to chime in as it's not in the data sheets for Gaisler. That's suspicious: either the numbers are bad or they leave it off given its meant for customization. Anyway, the Leon4...

http://www.gaisler.com/index.php/products/processors/leon4?t...

...uses 30,000 gates per core. Same ballpark as ARM and MIPS. Power use should be similar or at least acceptable if comparing ARM, MIPS, and Leon on same ASIC process. They often do rad-hard given it makes it resistant to SEU errors. That takes plenty of extra circuitry. Numbers I have for those, the high end, are 15mW per 1Mhz for Leon3RadHard and for Leon4RadHardQuadCore max was 6watts per one slideshow.

I'll take 6watts consumption in a router in exchange for quad-core, IOMMU-enabled, fault-tolerant, open CPU. What about you? Would 6 watts kill it for you?




Power consumption is of course very much dependent on the chosen fabrication process and SoC configuration. A LEON3/4 core is comparable to something like a ARM Cortex-M7 and it is not the ISA (when comparing ARMv7 vs SPARCv8) but the implementation that will affect power most. LEON is quite small and power efficient.


Node selected for fabrication does not equalize power consumption. You could go to the same node with other, inherently more power efficient architecture and gain even more oomph per watt. Power efficiency stems from the architecture itself; manufacturing process is a red herring (and a costly one). What you're saying is pretty much like "seasoned bodybuilder would kick white-belt karate practitioner's ass, so it's clear that bodybuilding is better than karate."

Compare things that are alike. If you take a manufacturer (say: TSMC), pick its node (say: 16nm FF+) and you decide on a package (physical manifestation of RTL primitives in the silicon) you get better performance per watt on one architecture over some other. ARM and MIPS are inherently very power efficient. You can't just take SPARC and make it more power efficient than these two. It doesn't work like that.

It's also not true that ISA doesn't matter. ISA impacts bandwidth requirements heavily. This in turn impacts latency and latency hiding, cache requirements and many other things. In fact data transfer is typically as costly as (if not more expensive than) computation. Getting data to all the right places on the schedule eats power like crazy. This is exactly why ARM has Thumb. It's not like internally core does different things than it would do with wide ISA. It's just that stuff's more densely packed, which helps tremendously.

Which brings me to my last point. There's an open architecture that's quite nice. It's SuperH (or SH2 in its open source form), which in turn is what ARM's Thumb is based on. It's not perfect, but it's pretty solid. Omitting it in the OP makes me think author isn't very thorough with his research. But everything has to start somewhere. ;)


I said fabrication process AND RTL architecture matters more than ARMv7 vs SPARCv8. They are both quite nice RISC architectures. Nothing in either one is especially power hungry.

Sure you have Thumb, that saves a little on memory bandwidth which is good. But nobody uses it anyways, and you might run slower so you can't sleep as fast.

I like the J2 (the open source sh) project as well but it doesn't have a MMU which rules it out for anything but simpler embedded projects.


> I'll take 6watts consumption in a router in exchange for quad-core, IOMMU-enabled, fault-tolerant, open CPU.

The router vendor surely looks at the cost of the CPU - ARM and MIPS cores are probably much cheaper.


Remember, I mentioned the SOC vendors as well. They currently license MIPS and ARM. Many choose MIPS due to cheap license. ARM's license, royalties, and restrictions are ridiculously expensive. SPARC has a cost advantage over it. So, once again, it's neither energy nor costs that are reasons they chose MIPS and ARM over SPARC.

Keep guessing.


I'm not so sure: Because currently ARM processors are currently sold in a large volume (if not for a technical reason then by momentum) they can be made a cheaper by economy of scale. This does not mean that this has to stay in the future, but currently this seems to be the case.


Now there's a good argument. Here's the real value, though, straight from ARM themselves: the ecosystem. They've built a whole ecosystem of boards, firmware, software, everything around ARM you get when you license their tech. It might be cheaper with economy of scale as well although licensing and royalties have to factor in. I'd default on MIPS there since they can be up to 10x cheaper than ARM. But yeah, a Freescale iMX ARM was like $4 per 100 units last time I looked it up.

So, it's mainly the ecosystem with companies and FOSS people wanting to benefit from what's already there instead of improve FOSS HW ecosystems. There's currently, but not indefinitely as you said, a cost advantage for the mass market SOC's as well for PPC, ARM, MIPS, and possibly SuperH.


> a Freescale iMX ARM was like $4 per 100 units last time I looked it up.

$4 per 100 units (4 pennies each), or $4 per unit in quantity of 100?




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